Clock generator devices (such as phase-locked loops (PLLs), frequency-locked loops (FLLs), clock and data recovery (CDR) devices, delay-locked loops (DLLs), etc.) have been widely used in integrated circuits of various fields. When designing a clock generator device, a loop bandwidth thereof is an important factor that will influence various performances thereof (such as stability, lock speed, noise, etc.). The loop bandwidth is generally designed to be within a range from one hundredth to one tenth of a frequency of an input clock signal received by the clock generator device. For each of various application specifications, a designer must redesign various loop parameters of the clock generator device to meet the design requirement of the loop bandwidth. Process, voltage and temperature (PVT) variations will occur during manufacture and operation of an integrated circuit that includes the clock generator device. As a consequence, the loop bandwidth will deviate from the designed value to undermine the performances of the clock generator device. Even worse, the loop bandwidth may deviate beyond the aforesaid range to make the clock generator device unstable and inoperable.